Connecting multiple test access port controllers on a single test access port

ABSTRACT

Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register ( 212 ) of each of a plurality of TAP controllers ( 102, 106 ), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. provisional application Ser.No. 60/435,395 filed 20 Dec. 2002, which is incorporated herein byreference.

BACKGROUND OF THE INVENTION

The present invention relates generally to electronic systems, and moreparticularly relates to methods and apparatus for connecting multipletest access port controllers on a single integrated circuit through asingle test access port.

Advances in semiconductor manufacturing technology, as well as indigital systems architecture, have resulted in the ability to design andproduce larger integrated circuits incorporating much more functionalitythan has been possible in the past. A particular class of integratedcircuits, which incorporate at least several large functional blocks toproduce a high level of functionality, is referred to as System on Chip(SoC). Such SoC integrated circuits often include one or more processorsalong with memory for storing program code that is to be executed by theprocessors, and one or more circuit blocks for implementing varioushigh-level peripheral functions. Such large, complex, and highlyfunctional integrated circuits present many challenges in terms ofdesign effort and testing.

In order to reduce the amount of time and effort required to design acomplex integrated circuit such as a SoC, engineers often attempt tore-use functional blocks (sometimes referred to as IP cores). Indeed,many design groups maintain libraries of such pre-designed andpre-verified IP cores. To maintain the advantages of using suchpre-designed and pre-verified IP cores, it is preferable to not have tomodify the internal design of such cores.

In order to address the requirements for testability, a number ofefforts have led to the development of test architectures, such as theJTAG specification which has been formalized by the Institute ofElectrical and Electronic Engineers as IEEE Standard 1149.1 Test AccessPort and Boundary Scan Architecture. Test access is provided to a wholeintegrated circuit, or a portion thereof, through a test access port(TAP) controller along with a variety of registers. A TAP controller maybe associated with each of a plurality of large functional blocks, suchas, for example, IP cores.

Some pre-designed IP cores may include TAP controllers, in otherinstances TAP controllers must be added to an integrated circuit designby the engineers as the one or more IP cores are included in a productdesign.

What is needed are methods and apparatus for accessing multiple testaccess port controllers on a single integrated circuit.

SUMMARY OF THE INVENTION

Briefly, embodiments of the present invention provide circuits andmethods for accessing multiple test access port (TAP) controllers on asingle chip, which is important for compliance with the IEEE 1149.1Standard. Embodiments of the present invention achieve compliance bymaintaining the appearance of having only a single test access port toan outside observer. By adding a single bit to a data register of eachof a plurality of TAP controllers along with straightforwardcombinational glue logic, the plurality of TAP controllers can beaccessed without the need for additional chip pins, and without the needfor additional TAP controllers that are arranged in a hierarchy ormaster-slave combination.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high-level schematic block diagram of a SoC that includes apair of IP cores, each having associated TAP controller/JTAG circuitry,and the logic and external connections for switching between each of thepair of IP cores for test access.

FIG. 2 is a high level block diagram of a SoC that includes a pair of IPcores, each having an associated switch register in accordance with thepresent invention, and the logic for internally generating a signal usedin switching between each of the pair of IP cores for test access.

FIG. 3 is a high-level schematic block diagram of a SoC having a pair ofTAP controllers illustrating the daisy chained data flow therebetween,in accordance with the present invention.

FIG. 4 is a schematic diagram of logic for implementing the daisychained data flow illustrated in FIG. 3, and the switching mechanismbased on the mode signal.

FIG. 5 is a high-level schematic block diagram of showing conventionalJTAG registers along with the switch register and chain register of thepresent invention.

FIG. 6 is a flowchart of an illustrative process in accordance with thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS.

When a design includes a plurality of IP cores and associated TAPcontrollers, it is desirable to be able to control which TAP controlleris enabled communicate with an outside observer. It is also desirable toaccess the multiple TAP controllers while remaining compliant with theIEEE 1149 specification, and without adding additional pins to theintegrated circuit. Various embodiments of the present invention allowmultiple TAP controllers on a single integrated circuit to be accessedin a controlled manner through a single TAP controller by including abit in a data register of each of the TAP controllers, along with simplecombinational logic. Addition of such user data registers is allowed inaccordance with the IEEE 1149 specification.

Reference herein to “one embodiment”, “an embodiment”, or similarformulations, means that a particular feature, structure, operation, orcharacteristic described in connection with the embodiment, is includedin at least one embodiment of the present invention. Thus, theappearances of such phrases or formulations herein are not necessarilyall referring to the same embodiment. Furthermore, various particularfeatures, structures, operations, or characteristics may be combined inany suitable manner in one or more embodiments.

Terminology

The acronym ASIC refers to Application Specific Integrated Circuit.

The expression “IP core” is context sensitive and may refer to either adesign for a high-level functional block (e.g., schematic, hardwaredescription language, netlist), or to an actual physical implementationof the high-level functional block. IP cores may include, in addition tothe circuitry for implementation of the desired function, circuitry forimplementation of test and debug facilities.

The acronym JTAG refers to the Joint Test Action Group. The Institute ofElectrical and Electronic Engineers (IEEE) has approved IEEE Standard1149.1, Test Access Port and Boundary Scan Architecture.

The acronym SoC refers to a System on a Chip, with SoCs being the pluralof SoC.

The terms chip, semiconductor device, integrated circuit, LSI device,monolithic integrated circuit, ASIC, SoC, microelectronic device, andsimilar expressions are sometimes used interchangeably in this field.Microelectronic device may be considered to be the broadest term,encompassing the others. With respect to these microelectronic devices,signals are coupled between them and other circuit elements viaphysical, electrically conductive connections. The point of connectionis sometimes referred to as an input, output, terminal, line, pin, pad,port, interface, or similar variants and combinations.

A JTAG compliant device includes pins for clock, input data, outputdata, and mode selection, referred to, respectively, as TCK, TDI, TDO,and TMS. TCK refers to Test Clock Input which is a terminal of the JTAGcompliant device that receives a clock signal separate from the systemclock. TDI refers to a Test Data In which is a terminal through whichdata is shifted into the JTAG compliant device. TDO refers to Test DataOut which is a terminal through which data is shifted out of the JTAGcompliant device. TMS refers to Test Mode Select which is a terminalwhich receives data for determining which of one or more test modes inwhich the JTAG compliant device is to operate. A JTAG compliant devicemay be any type of integrated circuit such as, for example, amicroprocessor, an ASIC, or a SoC. A JTAG compliant device may alsoinclude a pin to receive a low active reset signal, referred to asTRST#. JTAG compliant devices include a boundary scan register and a TAPcontroller. The TAP controller is a state machine that controls the JTAGfunctions. The boundary scan register is made up of a number of seriallyconnected bits where each of those bits is also coupled to digital pinsof the JTAG compliant device. JTAG compliant devices may also includeother registers, such as, a data register, an instruction register, anda bypass register.

The logical facilities defined by the IEEE 1149.1 specification arecommonly used for boundary scan testing and for system debug.

Various embodiments of the present invention provide a mechanism foraccessing one or more of the multiple TAP controllers within a SoC,while maintaining compliance with the IEEE 1149.1 specification. Simpleembodiments of the present invention allow a programmable switch from adefault TAP controller to a second TAP controller. In this way the stateof a SoC, as observed from outside the SoC, is compliant with the IEEE1149.1 specification at start-up (i.e., after a reset has been appliedto the system). More complex embodiments allow for arrangements such asswitching back and forth between individual TAP controllers; anddaisy-chaining all the TAP controllers together.

An application of the present invention is to provide access to multipleTAP controllers on a single chip while complying with the standard setforth in the IEEE 1149.1 specification. In turn, each TAP controllercontrols the test-logic (e.g., boundary scan testing) or the debugfeatures of an associated IP core. In accordance with the presentinvention, no additional controllers (e.g., top-level TAP, hierarchicalTAP, Master TAP, or TAP Linking Module) and no additional pins areneeded to force a particular mode of operation on the chip. Embodimentsof the present invention are programmable through, for example, thestandard JTAG ports. Embodiments of the present invention areparticularly useful in situations where the design of the TAPcontrollers and the IP cores are done separately, or at different pointsin time. Some embodiments of the present invention advantageouslyprovide a modular, scalable approach to integrating multiple TAPcontrollers into a SoC.

To understand the context of the present invention, refer to FIG. 1, andconsider that an IP integrator wishes to put two or more IP cores on oneSoC. The IP cores could be processors, DSPs, highly integratedfunctional blocks, or any combination of the foregoing.

Assume that each of these IP cores has a TAP controller and anassociated JTAG module arranged in such a way that this TAP-JTAGcombination forms an IEEE 1149.1 compliant device if it were on a chipby itself. A straightforward implementation for observing the two IPcores through a JTAG interface would use logical gating, multiplexing,and a “mode” pin as shown in FIG. 1.

Referring to FIG. 1, assume that TAP1 102 is the default TAP controllerand that the mode signal received from a mode pin 104 is set to zero atstart-up. Note that both the TDI and TMS inputs to TAP1 102 and TAP2 106are logically gated such that when the mode signal is a logical zero,TAP1 102 receives the actual TDI and TMS signals while TAP2 106 receiveszeroes for those inputs; and when the mode signal is a logical one, TAP2106 receives the actual TDI and TMS signals while TAP1 102 receiveszeroes for those inputs. The physical implementation of such logiccircuitry is a matter well understood by those skilled in the art. It isnoted that the only output from either TAP1 102 or TAP2 106 is TDO. Theother pins of TAP controllers 102, 106 are inputs. It is also noted thatthe finite state machine (FSM) of the TAP controllers 102, 106 willdefault to the Run-Test-Idle state within five cycles of the clocksignal received on the TCK pin if the signal received from the TMS pinis zero. The TDI, TCK, TRSTN signals may be freely shared among TAPcontrollers 102, 106 (but TDI in addition to TMS are logically gated asshown in FIG. 1).

The TDO outputs are multiplexed by a 2-to-1 multiplexer 108, as are thetwo enable signals (not shown) for the tri-state buffer associated withthe TDO outputs. It is not an uncommon practice that the TAP controller,JTAG module, and IP core are designed separately, and at differentpoints in time. The IP integrator has the task to connect thestandardized interfaces properly.

Referring to FIG. 2, assume that each JTAG module 202, 204 containsseveral JTAG registers, such as, for example, an instruction register206, a bypass register 208, and an IDCODE register 210. The IEEE 1149.1standard allows extending JTAG modules 202, 204 by user-defined dataregisters. In various embodiments of the present invention, a one bitdata register 212 is added to at least the default TAP controller. Sucha one bit data register is referred to herein as the switch register212. FIG. 2 shows a switch register 212 incorporated into each of thetwo JTAG modules 202, 204 of this illustrative embodiment of the presentinvention. The outputs of each of the one bit switch registers 212 arecoupled to an XOR gate 214 to produce the mode signal that controls thelogical gating and multiplexing shown in FIG. 1. That is, the modesignal which is produced within the integrated circuit, in accordancewith the present invention, replaces the externally supplied modesignal, and corresponding mode pin, shown in FIG. 1.

In accordance with the present invention, the two TAP controllers willappear to be one TAP controller to an off-chip observer, such as a JTAGprobe. This is because the state that updates a data registertransitions into the Run-Test-Idle state with one more high-level valueon TMS during a TCK clock edge. While the probe is negotiating the JTAGprotocol, the hardware reconfigures itself and a different TAPcontroller is connected to the external interface pins of the SoC. Thefact that the protocol can be used during this particular statetransition for the purpose of changing the connections of the TAPcontrollers themselves is used by embodiments of the present invention.

The nature of JTAG operations is that a new value is shifted into aregister while, typically, the old value is shifted out and capturedoff-chip. In some cases a different value is shifted out, for example,when shifting in a new instruction. In order to have a uniformpredictable switching mechanism across multiple JTAG modules, it isdesirable that a JTAG probe should not be required to keep track of thecurrent values for different switch registers 212. Therefore, in anembodiment of the present invention, the content of switch register 212is inverted when shifting in a logical one. So regardless of the currentvalues of both switch registers 212, if exactly one input is inverted,the mode signal will switch. Such an arrangement is suitable forembodiments of the present invention in which two TAP controllers areintegrated in a single chip.

Given that it is possible, in accordance with the invention, to switchback and forth between two TAP controllers, it is further desirable toprovide for daisy chaining of the TAP controllers. In one illustrativeembodiment of daisy chaining, as shown in FIGS. 3 and 4, the techniqueshown in FIG. 2 is extended to provide the data-flow associated daisychaining. More particularly, the general data flow associated with daisychaining is shown in FIG. 3 by only presenting the flow from TDI to TDO.To accomplish daisy chaining in accordance with the present invention, aTAP controller (e.g., TAP1 102) is further extended by a one bit dataregister, referred to hereafter as the chain register. FIG. 5illustrates the conventional instruction, bypass, and IDCODE JTAGregisters 206, 208, 210, and the switch and chain registers 212, 502 ofthe present invention.

It is noted that although it is possible to add chain bits to more thanone of the plurality of TAP controllers on a single integrated circuitin accordance with the present invention, this increases the complexityof the combinational logic that is required for control. It will beappreciated that those skilled in the art and having the benefit of thisdisclosure can readily synthesize such control logic and therefore thosedetails are not described further.

As indicated in FIG. 4, the chain signal can now be used in addition tothe mode signal to implement appropriate logical gating and multiplexingfor TDI1, TDI2, TDO1 and TDO2. Assuming that mode=0 when chain=1, thenFIG. 4 is logically equivalent to FIG. 3. It will be appreciated thatthis is an illustrative embodiment of the present invention, and thatthe exemplary logic may be different if the value of the mode signal,for example, is chosen to be different. This is well-understood by thoseskilled in the art.

FIG. 6 illustrates a process flow in accordance with the presentinvention. Switch register bits in two or more TAP controllers are reset602 to a known state. A logical combination of the outputs of the switchregister bits in their reset state controls which of the TAP controllerscan be accessed by an external observer. Subsequently, writing to theswitch register bit of the selected TAP controller results in that bittoggling (i.e., having its current state inverted). The new state of theswitch register bits is used to produce, or derive, 604 at least onemode signal. Based at least in part on the state of the mode signal(s),a next TAP controller is selected 606 for communication with theexternal observer. In the case of two TAP controllers, the mode signalalways selects one of the two TAP controllers.

In order to scale beyond two TAP controllers a mode bus may be derived,such that a changing value in any switch-register causes the nextscheduled TAP controller to be selected. Such examples are described ingreater detail below.

In the following section an illustrative embodiment having three TAPcontrollers (referred to as TAP1, TAP2, and TAP3) is described. Each TAPcontroller has a 1-bit switch register that resets to zero. Instead ofusing a single XOR to make the mode bit (as described above inconnection with the example having two TAP controllers), a mode bus isused.

With respect to switching between TAP1, TAP2, and TAP 3, assume around-robin scheduling algorithm is implemented to provide accessbetween all the TAP controllers. (It is noted that selecting one out ofmany TAPs is a different function than chaining, and each of thesefunctions is desirable for different purposes. Various embodiments ofthe present invention support both selecting and chaining.) In thisillustrative embodiment TAP1 is selected by default, and when the switchregister of a selected TAP controller is written, a next controller isselected, for example: TAP1->TAP2->TAP3->TAP1 and so on. The mode-bushas a width corresponding to ceiling[log 2(#TAPs)], which, in thisillustrative embodiment, amounts to two bits, and those two bits may bedefined as shown in TABLE 1.

TABLE 1 mode[1:0] selected TAP 00 TAP1 01 TAP2 10 TAP3 11 not used

The logic for the mode-bus is solely dependent on the value of the threeswitch register bits, S1, S2 and S3, as shown in TABLE 2.

TABLE 2 select, inputs S3 S2 S1 mode output Operation in this mode: 0 00 TAP, 00 S1 switch makes input = 001 0 0 1 TAP2, 01 S2 switch makesinput = 011 0 1 1 TAP3, 10 S3 switch makes input = 111 1 1 1 TAP1, 00 S1switch makes input = 110 1 1 0 TAP2, 01 S2 switch makes input = 10 1 0 0TAP3, 10 S3 switch makes input = 000 others not used remaining inputcombinations not used

In this illustrative embodiment, the TDI and TMS inputs are gated by a3-input AND gate (see TABLE 1). Two of the inputs are the mode[1] andmode[0] bits, with some inverting, such that only the selected TAPcontroller receives a TDI or TMS signal from the top-level pins.Similarly, the three TDO signals are multiplexed using the mode[1:0]bits such that only the selected TAP controller provides a TDO signal tothe top-level pins. Various well-known circuits can be used to implementthe foregoing logic and multiplexing. The input-output table (see TABLE2) for the mode-bus can be easily synthesized and yields an relativelysmall number of logic gates.

In the following section an illustrative embodiment having four TAPcontrollers (referred to as TAP1 to TAP4 in this example) is described.

With respect to switching between the various TAP controllers, assumeround-robin scheduling is implemented between all TAP controllers. Inthis illustrative embodiment TAP1 is selected by default. When theswitch register of the selected TAP controller is written, a nextcontroller is selected, for example: TAP1->TAP2->TAP3->TAP4->TAP1 and soon.

In the illustrative embodiment the mode-bus has a width corresponding toceiling[log 2(#TAPs)] (which still amounts to two bits), and the modebits are defined in TABLE 3.

TABLE 3 selected TDO (mode-bus mode[1:0] selected TAP is input to 4-to-1mux) “00” TAP1 tdo1 “01” TAP2 tdo2 “10” TAP3 tdo3 “11” TAP4 tdo4

The logic for the mode-bus is solely dependent on the value of the fourswitch register bits, S1, S2, S3 and S4, as shown in TABLE 4.

TABLE 4 select, inputs S4 S3 S2 S1 mode output Operation in this mode 00 0 0 TAP1, 00 S1 switch makes input = 0001 0 0 0 1 TAP2, 01 S2 switchmakes input = 0011 0 0 1 1 TAP3, 10 S3 switch makes input = 0111 0 1 1 1TAP4, 11 S4 switch makes input = 1111 1 1 1 1 TAP1, 00 S1 switch makesinput = 1110 1 1 1 0 TAP2, 01 S2 switch makes input = 1100 1 1 0 0 TAP3,10 S3 switch makes input = 1000 1 0 0 0 TAP4, 11 S4 switch makes input =0000 others not used remaining input states not used

It is noted that there are a number of unused input combinations (alsoreferred to as input states).

In this illustrative embodiment, the TDI and TMS inputs are gated by a3-input AND gate (see TABLE 3). Two of the inputs are the mode[1] andmode[0] bits, with some inverting, such that only the selected TAPcontroller receives a TDI or TMS signal from the top-level pins.Similarly, the four TDO signals are multiplexed using the mode[1:0] bitssuch that only the selected TAP controller provides a TDO signal to thetop-level pins. Various well-known circuits can be used to implement theforegoing logic and multiplexing.

If more TAP controllers are to be used, then the number of mode bitsgrows with log 2 rate. That is, three mode bits are sufficient for up toeight TAP controllers, four bits are sufficient up to sixteen TAPcontrollers and so on. The number of defined and used input states alsogrows slowly, only by two states per added TAP controller.

With respect to chaining between the various TAP controllers, ratherthan switching as described above, the following changes are needed:every TDI in a chain is configured to receive its signal from twosources, namely: (1) the top-level TDI pin in case it is the TDI of theselected TAP controller, or, the TDO-signal from the preceding TAPcontroller in case of chaining. There are small provisions at thebeginning and the end of the chain, but the complexity does not growwith the addition of more TAP controllers. For example, even with achain containing ten TAP controllers, the TDI for any TAP controller inthe chain can still only come from two possible sources, which are, asnoted above: (1) the top-level TDI for the case of being the TDI of theselected controller, or, (2) from the TDO signal of the preceding TAPcontroller for the case of being a TDI of a daisy-chained TAPcontroller. Similarly, in this illustrative example, the TDO pin iseither driven by an individual selected TAP controller (using an n-to-1multiplexer), or, if all TAP controllers are daisy-chained, the TDO isdriven by the TDO-signal from the last TAP in the chain.

Embodiments of the present invention may use scheduling algorithms otherthan round-robin, although there are some complexity issues in makingthe target of a switch programmable. In such a scenario, the state ofthe system may be stored in every TAP controller, or in a central place.This is different from the above-described illustrative embodimentswherein the state is encoded in the combined switch/chain bits of thedata registers in the TAP controllers.

CONCLUSION

Multiple test access port (TAP) controllers on a single chip areaccessed, in accordance with the IEEE 1149 specification by maintainingthe appearance of having only a single test access port to an outsideobserver. By adding a single bit to a data register of each of aplurality of TAP controllers, along with straightforward combinationalglue logic, the plurality of TAP controllers can be accessed without theneed for additional chip pins, and without the need for additional TAPcontrollers. By adding a second bit to at least one of the TAPcontrollers, internal derivation of signals suitable for controllingdesirable functionality of the plurality of TAP controllers can beachieved. Toggling the state of the added bits in the respective dataregisters of the plurality of TAP controllers provides the controlinformation for either switching or daisy-chaining of the plurality ofTAP controllers.

It is to be understood that the present invention is not limited to theembodiments described above, but encompasses any and all embodimentswithin the scope of the subjoined claims.

1. A method of coupling a plurality of test access port (TAP)controllers to a single external interface, comprising: a) resetting afirst bit in each of a plurality of TAP controllers to a known state; b)producing a first signal based, at least in part, on the state of thefirst bit in each of the plurality of TAP controllers; c) selecting oneof the plurality of TAP controllers based, at least in part, on thefirst signal; d) coupling an external input terminal to an inputterminal of the selected one of the plurality of TAP controllers; and e)coupling an output terminal of the selected one of the plurality of TAPcontrollers to an external output terminal.
 2. The method of claim 1,wherein the TAP controller comprises a finite state machine and aplurality of registers.
 3. The method of claim 2, further comprisingentering a run-test-idle state by toggling the first bit in the selectedone of the plurality of TAP controllers; and while in the run-test-idlestate, selecting a second one of the plurality of TAP controllers basedon the state of the first bit in each of the plurality of TAPcontrollers; coupling the external input terminal to an input terminalof the second TAP controller; and coupling an output terminal of thesecond TAP controller to the external output terminal.
 4. The method ofclaim 3, further comprising providing a clock signal, a test modeselection signal, and a test reset signal to each of the plurality ofTAP controllers.
 5. The method of claim 3, wherein the plurality of TAPcontrollers are disposed on a single integrated circuit.
 6. The methodof claim 5, wherein the first signal is produced within the singleintegrated circuit.
 7. The method of claim 6, further comprisingreceiving, from a source external to the single integrated circuit, aclock signal.
 8. An integrated circuit, comprising: a plurality offunctional blocks, each functional block having a test access port (TAP)controller coupled thereto; each TAP controller including a firstregister bit, each first register bit adapted to produce a known outputstate in response to a reset signal, each first register bit furtheradapted to toggle in response to a register write operation; and routinglogic adapted to selectively provide, based at least in part on thestate of the plurality of first register bits, a communication pathbetween an external input signal source and an input terminal of aselected one of the TAP controllers, the routing logic further adaptedto provide, in response to toggling of the first register bit in theselected TAP controller and based on the state of each of the firstregister bits, a communication path between the external input signalsource and an input terminal of a second one of the TAP controllers. 9.The integrated circuit of claim 8, wherein the routing logic is furtheradapted to selectively provide, based at least in part on the state ofthe plurality of first register bits, a communication path between anexternal output terminal and an output terminal of the selected TAPcontrollers, and the routing logic is further adapted to provide, inresponse to the toggling of the first register bit in the selected TAPcontroller and based on the state of each of the first register bits, acommunication path between the external output terminal and an outputterminal of the second TAP controller.
 10. The integrated circuit ofclaim 9, wherein a transition between the selectively providedcommunication paths is transparent to an external observer.
 11. Theintegrated circuit of claim 8, wherein at least one TAP controllerfurther includes a second register bit; wherein the routing logic isfurther adapted to provide the output of a first TAP controller as aninput to a second TAP controller, based at least in part on the state ofthe first and second register bits.
 12. An integrated circuit (IC),comprising: a plurality of test access port (TAP) controllers disposedon the IC, each of the plurality of TAP controllers having a first inputterminal adapted to receive a data input signal and an output terminaladapted to provide a data output signal, each of the plurality of TAPcontrollers further having at least one switch bit; a first interface toreceive an externally supplied input signal; a second interface totransmit an internally generated output signal; and routing logicadapted to selectively provide, based at least in part on the state ofthe switch bits of the plurality of TAP controllers, a firstcommunication path between the input terminal of a predetermined one ofthe plurality of TAP controllers and the first interface, and a secondcommunication path between the output terminal and the second interface.13. The integrated circuit of claim 12, further comprising a pluralityof functional blocks coupled respectively to each of the plurality ofTAP controllers, wherein the routing logic is further adapted toprovide, in response to toggling of the switch bit in the predeterminedTAP controller and based on the state of each of the switch bits, afirst communication path between the input terminal of a second one ofthe plurality of TAP controllers and the first interface, and a secondcommunication path between the output terminal of the second TAPcontroller and the second interface.
 14. The integrated circuit of claim13, wherein the each of the plurality of TAP controllers has a secondinput terminal adapted to receive a clock signal, a third input terminaladapted to receive mode select signal, and a fourth input terminaladapted to receive a reset signal; wherein the plurality of second inputterminals are coupled in common, the plurality of third input terminalsare coupled in common, and the plurality of fourth input terminals arecoupled in common.
 15. The integrated circuit of claim 14, furthercomprising a chain bit disposed in a first one of the plurality of TAPcontrollers.